View MIL-STD-1553B_4448142.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CT1775 Universal MacAir/1553 Dumb RTU Hybrid
PRELIMINARY DATA SHEET
www.aeroflex.com/Avionics FEATURES

CT1775 Replaces DDC BUS-65201 Includes: - Universal Transceiver - Encoder/decoder - Dual Rank I/O Registers - Fail-safe Timer - Clock Oscillator Simple Controls for Single or Dual Redundant Data Bus Configurations Provides Flags for: - Own Address (With Parity) - Mode Code - Broadcast - Time Out - Valid Word - Sync Type 16 Bit or 8 Bit 3-State - Parallel I/O and Serial Out Wraparound Built-In Test MIL-PRF-38534 Compliant Circuits Available Packaging - Hermetic Metal - 68 Pin, 1.85" x 1.6" x .19" Plug-In Type Package

DESCRIPTION
The CT1775 Universal MACAIR/1553 Dumb Remote Terminal Unit (RTU) consists of a transceiver, and encoder/decoder, control logic, dual rank I/O registers and internal clock oscillator packaged in a 1.6" x 1.9" hermetic hybrid. It provides all the functions required to interface between a MACAIR (sinusodial) or MIL-STD-1553 (Trapezoidal) serial MUX data bus and a subsystem parallel 3-state data highway. Utilizing several ASIC ICs, the CT1775 provides sufficient handshaking, control and data lines to permit versatile operation as a remote terminal, a bus controller or a bus monitor, in either single or dual redundant data bus configurations. As a transmitter, the CT1775 accepts 8 bit or 16 bit parallel date from the subsystem, and outputs serial Manchester II coded Command, Status or Data words, under subsystem control. As a receiver, it accepts serial MIL-STD-1553 or MACAIR transmissions and transfers all Command, Status and Data words to the 8 bit or 16 bit data highway, under subsystem control. The CT1775 also provides flags to the subsystem when Broadcast, Mode Code, and Own Address (with parity) commands are decoded. The CT1775 contains a terminal fail-safe timeout circuit which flags message lengths exceeding 768s, and terminates serial data transmission. Wraparound selftest is initiated by a control line which causes the encoder serial output to be connected to the decoder input. The CT1775 provides a serial output of decoded words, thus allowing Command Word look ahead, for the fastest terminal response.
SCDCT1775 Rev B
TX DATA
SHAPING NETWORK
ENCODER AND CONTROL LOGIC REGISTER SERIAL DATA IN REGISTER
CHAN SELECT BDST INHIBIT BROADCAST MODE CODE VALID WORD MANCHESTER VAL CMD WD FAIL-SAFE COMM DATA SYNC RTENABLE PARITY SERIAL DATA OUT BIT STATUS SERIAL DATA OUT REGISTER REGISTER FAILSAFE DRIVER
DRIVER
RX DATA FILTER DECODER AND CONTROL LOGIC
LIMITER
RX DATA
CLOCK GEN CLOCK OUT XTAL MRST DEC RST CLOCK IN RX STROBE 5
CLOCK POWER
DATA SELECT1 DATA SELECT2
TAKE ENA ADDR DATA ADDR IN PAR S/T DSC ADDR SELECT OUT PAR IN
FIGURE 1 - CT1775 BLOCK DIAGRAM
}
DATA
SCDCT1775 Rev B ENC ENABLE SYNC SELECT ESC SEND OUT DATA LOAD LOAD DATA1 DATA2 LATCH LATCH DATA1 DATA2 SHAPING NETWORK MANCHESTER T/O D15 (MSB) THRU D0 (LSB)
TX INHIBIT
TX DATA
DRIVER
}
2
VALUES AT NOMINAL POWER SUPPLY VOLTAGES UNLESS OTHERWISE SPECIFIED
PARAMETER Receiver Differential Input Impedance (DC to 1MHz) Differential Input Voltage Input Threshold (Direct Coupled) CMRR (DC to 2MHZ) CMV (DC to 2MHZ) RX STROBE Characteristics Transmitter Differential Output Voltage Direct Coupled (across 145 Load) Transformer Coupled (at stub) Output Rise and Fall time Output Noise TX INHIBIT Characteristics Logic IIH, IIL, IOH, IOL VOH VOL VIH VIL Clock VOHC (Internal Clock) VOLC (Internal Clock) VIHC (External Clock) VILC (External Clock) Power Supplies +5V OSC/CLOCK Supply Voltage Tolerances Current Drain +5V Logic Supply Voltage Tolerances Current Drain +15V (or +12V) Supply Voltage Tolerances Current Drain -15V Supply Voltage Tolerances Current Drain Idle 25% Transmit 100% Transmit -12V Supply Voltage Tolerances Current Drain Idle 25% Transmit 100% Transmit Temperature Range Operating (Case) Storage Physical Characteristics Size 68 pin DDIP
SCDCT1775 Rev B
VALUE
UNITS
4 min 40 max 1 typ 40 min 10 min 1 typ
K VP-P VP-P dB V TTL Loads
30 typ 21 typ 130 typ 10 max 1 typ See pin function & loading Table 2.5 min 0.4 max 2.0 min 0.7 max Supply -0.3 min Ground +0.3 min Supply -0.5 min Ground +0.5 min
VP-P VP-P ns mVP-P TTL Loads
V V V V V V V V
10 8 typ; 13 max 10 250 max 5 65 max 5 65 max 105 max 250 max 5 65 max 105 max 250 max -55 to +125 -65 to +150
% mA % mA % mA % mA mA mA % mA mA mA C C
1.6 x 1.9 x 0.18
in
TABLE 1 - CT1775 SPECIFICATIONS
3
GENERAL
As shown in the block diagram of Figure 1, the CT1775 provides all functions required to implement a Dumb Remote Terminal Unit (RTU). It is designed for the greatest flexibility and ease of use. CT1775 can be operated with either an internal or external clock. Simple control lines are provided to interface with either single channel or dual redundant configurations. Control lines are available to implement either on line or off line wraparound built-in test. CT1775 can be configured to perform a parity check on its hard-wired terminal address. It provides numerous output flags to simplify the use interface. These flags indicate various decoded messages, as well as the results of error checks. Sync selection, along with the flexible controls, allows the CT1775 to operate as a Bus Controller as well as a Remote Terminal.
DUAL REDUNDANT OPERATION
The CT1775 may be used in a dual redundant configuration with a minimum of additional circuitry. A CHAN SELECT signal is provided which simultaneously disables the LATCH DATA, DATA SELECT, and ENC ENABLE lines of the CT1775. Therefore, CHAN SELECT can be used to multiplex a single set of LATCH DATA, DATA SELECT and ENC ENABLE control signals between two CT1775 units, which have these signals tied together in parallel.
WRAPAROUND BUILT-IN TEST
The CT1775 may be configured to implement either on line or off line wrap around built-in test. By enabling the receiver with RX STROBE during a normal transmission, the encoded word will be fed back into the decoder by the receiver. In this on line wrap around mode of operation, the CT1775 compares each decoded word that is fed back with the original word that was encoded. The BIT STATUS output flag indicates when the two words are not the same. Care must be taken when using this on line wrap around test technique because an outgoing status word will be interpreted by the decoder as a new command word. Since the status word has the correct address and the same sync as a command word, the CT1775 will set RT ENABLE and VAL CMD WD. For on line wrap around operation, it is therefore necessary to reset RT ENABLE after transmission of a status word. This can be accomplished by inverting SEND DATA and applying it to DEC RST during status word transmission. If it is required that the status word be fed back, RT ENABLE should be reset immediately after it goes HIGH by applying a LOW to DEC RST for 1 microsecond (minimum). The status word will be available at the receive register. The CT1775 can be placed in an off line wrap around test mode by use of the S/T SELECT signal. In this mode, the transceiver is disabled and the encoder output is fed directly to the decoder input. All other functions remain the same, and the CT1775 compares each word that is decoded with the original word that was encoded. The BIT STATUS line also indicates the result of this comparison for the off line wrap around test.
INTERNAL OR EXTERNAL CLOCK
CT1775 may be operated with either its internal clock or an external clock. Internal clock operation requires that a 12 MHz parallel-resonant fundamental-mode crystal, such as MIL-C-3098/42 TYPE CR64/U, be connected between pin 18 (XTAL) and ground. In addition, +5 volt power must be connected to pin 2 (OSC/CLOCK POWER), and CLOCK OUT (pin 19) must be connected to CLOCK in (pin 24). For external clock operation, no connection is made to pin 2 (OSC/CLOCK POWER, and the external clock is applied to pin 24 (CLOCK IN). Pin 19 (CLOCK OUT) is not connected. The external clock must be capable of driving a load of 20 picofarads to within 0.5 volts of the + 5 volt power supply and to within 0.5 volts of ground. Standard TTL voltage levels will not work properly. It must have a rise time and fall time of less than 10 nanoseconds. For compliance with MILSTD-1553, the external clock frequency must be 12 MHz.
8 BIT OR 16 BIT INTERFACE
The CT1775 may be configured to interface with either 8 bit or 16 bit parallel data highways. For 16 bit operation, the 16 data lines (D 15 through DO) are used directly. LATCH DATA 1 and LATCH DATA 2 are tied together, as are DATA SELECT 1 and DATA SELECT 2. This allows data transfer in 16 bit bytes. For 8 bit parallel data highways, the 16 data lines must be tied together in eight pairs (1315 to D7, D8 to 130, etc.) The two LATCH DATA and DATA SELECT are used independently. This allows transfer in two 8 bit bytes.
FAIL SAFE TIME-OUT
The CT1775 contains a timer which continuously monitors the length of each transmitted message. This timer detects a transmitted message which exceeds 768 microseconds and causes the transmission to terminate. At the same time, The FAIL-SAFE flag is set to indicate a Terminal Fail-Safe Time-out. Further transmissions are inhibited until the FAIL-SAFE flag is reset by MRST or a valid command word with the correct address is received.
ADDRESS WITH PARITY
The CT1775 provides five lines for hard-wired terminal address. Internal pull-up resistors are provided on these lines, so logic "1" lines may be left open-circuited. Logic "0" lines must be grounded. The CT1775 maybe configured to check the parity of these five address lines. This function can be selected by using the ENA PAR CHECK line. The address parity line (TMADDP) is hard-wired for odd address parity if the function is sued. the ODD PARITY output flag indicates a valid check for odd parity of the six address lines.
SCDCT1775 Rev B
4
OUTPUT FLAGS
The CT1775 provides numerous output flags to offer the greatest user flexibility. VALID WORD indicates receipt of a word with valid sync, Manchester coding and parity. RT ENABLE indicates a valid word and correct address. VAL CMD WD indicates a valid word and a Command Sync. BROADCAST indicates a valid command word and an address of 11111. The BROADCAST flag may be inhibited by using the BDCST INHIBIT line. MODE CODE indicates a valid command word and a subaddress of 11111 or 00000.
For multiple word transmissions, the next word may be transferred to the transmit register any time after SEND DATA goes HIGH, but no later than the next LOW to HIGH transition of SEND DATA. SEND DATA remains HIGH for 16 periods of ESC OUT, during which time the data word is serially shifted to the Manchester encoder. The encoder adds the parity bit during the next ESC OUT period after SEND DATA goes LOW. To terminate transmission after any word, ENC ENABLE must go to HIGH no later than the first rising edge of ESC OUT after SEND DATA goes LOW. The entire transmit cycle may be interrupted and initialized by applying a 1 microsecond (minimum) negative pulse to MRST. It is possible to input data to the encoder in serial form by forcing both transmit registers to be transparent. With LATCH DATA 1 held HIGH and LOAD DATA 1 held LOW, serial data input on D15 will be applied directly to the encoder serial input. ESC OUT must be used to shift in the serial data, MSB first, starting at the LOW to HIGH transition of SEND DATA.
INITIALIZATION
To ensure error-free operation, it is desirable to reset the CT1775 to its initialized state upon power turn-on. The MRST (master reset) signal is provided for this purpose. Both the flecoder and encoder, as well as all flags, are reset by a LOW on MRST. This function interrupts and overrides all other control signals. The MRST function can also be sued during fault recovery routines.
DECODER OPERATION
Figure 3 illustrates the receive mode timing. Decoder detail timing is shown in Figure 5. A receive cycle, which lasts for 20 clock periods of the 1 MHz DSC OUT, is initiated when the decoder recognizes a valid sync and two valid Manchester data bits. TAKE DATA goes LOW at the first HIGH to LOW (falling edge) transition of DSC OUT, following the second valid dat bit. COMM/DATA SYNC is updated at the next rising edge of DSC OUT after TAKE DATA goes LOW. COM/DATA SYNC remains in its new state until the next valid word or until DEC RST or MRST goes LOW. TAKE DATA remains LOW for 16 periods of DSC OUT, during which time the 16 serial data bits are shifted into the first rank receive register. The serial data is simultaneously available at SERIAL DATA OUT as it is being shifted. At the completion of decoded data shifting, TAKE DATA goes HIGH, which transfers the data to the second rank receive register. This data may be enabled onto the parallel data highway by LOW on DATA SELECT at any time until the next rising edge of TAKE DATA. At the first rising edge of DSC OUT after TAKE DATA goes HIGH, VALID WORD is updated. It will go LOW if the decoded word was valid. VALID WORD will go HIGH at the start of the next receive cycle, or after 20 microseconds if no additional words ar received. All output flags are enabled by VALID WORD, and therefore they are valid only as long as VALID WORD is LOW.
TRANSCEIVER OPERATION
The CT1775 contains a transceiver similar to Aeroflex model CT3232. When connected to a serial MUX data bus via transformer and isolation resistors, as shown in Figure 6, the CT1775 transceiver will fully comply with MIL-STD-1553. The correct Technitrol part numbers for transformers used in direct-coupled and transformercoupled operation are shown in Figure 6. Transceiver TX INHIBIT and RX STROBE signals are provided to afford flexible operation. These signals may be used to disable the transmitter and receiver, respectively.
ENCODER OPERATION
Figure 2 illustrates the transmit mode timing. Encoder detail timing is shown in Figure 4. The transmit cycle is initiated by a LOW on ENC ENABLE. The first HIGH to LOW (falling edge) transition of ESC OUT, when ENC ENABLE is LOW, starts the cycle which lasts for 20 clock periods of the 1 MHz ESC OUT. The next LOW to HIGH transition of ESC OUT strobes the SYNC SELECT line. A HIGH on SYNC SELECT produces a data sync and a LOW produces a command/status sync. A LOW to HIGH transition of SEND DATA occurs at the fourth falling edge of ESC OUT. This indicates the completion of the sync interval and the start of the serial data interval. Parallel data must be stable at the second rank transmit register prior to the rising edge of SEND DATA, which occurs 3 microseconds (minimum) after the HIGH to LOW transition of ENC ENABLE. LATCH DATA is used to transfer parallel data to the first rank transmit register. LATCH DATA must be brought LOW and DATA SELECT brought HIGH prior to the rising edge of SEND DATA. If SEND DATA is connected directly to LOAD DATA, it will lock out the second rank transmit register and serial data shifting into the encoder will proceed properly.
SCDCT1775 Rev B
5
SERIAL DATA OUT
SYNC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
ESE OUT START CYCLE ENC ENABLE STROBE SYNC STROBE DATA
DON'T CARE
DATA SENT
END CYCLE
VALID SYNC SYNC SEL
DON'T CARE
16s SEND DATA (LOAD DATA)
LATCH DATA VALID DATA TRI-STATE DATA
DON'T CARE
DON'T CARE
DATA SELECT
DON'T CARE
FIGURE 2 - TRANSMIT MODE TIMING
SERIAL DATA IN
19 0
SYNC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
SYNC
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
1
2
3
4
5
DSC OUT START CYCLE TAKE DATA 16s COMM / DATA SYNC
PREVIOUS STATE CURRENT SYNC
TAKE DATA
STROBE DATA
END CYCLE
SERIAL DATA OUT
PREVIOUS STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UNDEFINED
15
DATA SELECT 1 CURRENT DATA TRI-STATE DATA 1
DON'T CARE
VALID WORD 2
PREVIOUS STATE
FLAG OUTPUTS 3
PREVIOUS STATE
NOT VALID
FLAGS VALID 3
BIT STATUS
4
NOT VALID
BIT STATUS VALID 4
NOTES: 1. Parallel data is held continuously in second rank receiver register, and may be enabled onto the tri-state output at any time with a LOW on DATA SELECT. 2. VALID WORD will remainLOW for 20sec then go HIGH, if a valid sync is not received. 3. FLAG OUTPUTS are valid only when VALID WORD is LOW. Flags are MODE CODE, RT Enable, BROADCAST and VAL CMD WD. 4. BIT STATUS is valid only if wraparound transmit plus receive cycle has been performed. LATCH DATA must be HIGH, and either S/T SELECT or RX STROBE must be HIGH for the full wraparound cycle duration.
FIGURE 3 - RECEIVE MODE TIMING
SCDCT1775 Rev B
6
19
0
1
2
3
4
ESC OUT
START CYCLE STROBE SYNC 110ns MAX STROBE DATA
ENC ENABLE
180ns MIN
190ns MIN
SYNC SELECT
240ns MIN 80ns MAX
SEND DATA (LOAD DATA)
80ns MIN
LATCH DATA
DON'T CARE 130ns MIN 80ns MIN
TRI-STATE DATA
DON'T CARE 100ns MIN 70ns MIN
DATA SELECT
DON'T CARE 130ns MIN
FIGURE 4 - ENCODER DETAIL TIMING
5
6
7
0
1
2
DSC OUT
100ns MAX 100ns MAX
TAKE DATA
150ns MAX
COMM / DATA SYNC
PREVIOUS
CURRENT SYNC
CURRENT
SERIAL DATA OUT
15
14
0
50ns MIN
DATA SELECT
50ns MAX
TRI-STATE DATA
DON'T CARE
CURRENT DATA
100ns MAX
VALID WORD
60ns MAX
MODE CODE
60ns MAX
RT ENABLE
100ns MAX
BROADCAST
110ns MAX
VAL CMD WD
FIGURE 5 - DECODER DETAIL TIMING
SCDCT1775 Rev B
7
SCDCT1775 Rev B
Z = 78
CT1775
51 67 7 *2 6 5 68 3 1 7 *2 5 4 3 1.4 : 1 21V P-P 2 3 1:1.41 .75 Z 6 8 1 4 49 55 Q1553-20 .75 Z 4 30V P-P 7V P-P Q1553-1 1:1 1 8 55
DIRECT COUPLED
TX DATA OUT RX DATA IN
TX DATA OUT
RX DATA IN
DATA BUS
8 * Transformer CT may be left open
Technitrol Part #'s Q1553-1 & Q1553-20
TRANSFORMER COUPLED
Z = 78
FIGURE 6 - TYPICAL TRANSFORMER CONNECTIONS
PIN FUNCTION AND LOADING TABLE PIN #
1 2 3 4 5
NAME
GND +5V OSC/ CLOCK POWER NC TX INHIBIT SYNC SELECT
IIH (A)
IIL IOH IOL (mA) (mA) (mA)
DESCRIPTION
Power supply and logic return. +5V Power for oscillator and clock driver. No connection.
20 20
-0.4 -0.4
A LOW on this input inhibits the transmitter. A LOW on this input results in a transmitted DATA sync. A HIGH on this input results in a transmitted COMMAND (or STATUS) sync. -0.4 -0.4 4.0 4.0 Received serial data in NRZ format is available at this output when TAKE DATA is LOW. LOW to HIGH transitions on this output when SEND DATA is HIGH causes the transmit cycle data shifting to occur. No connection. -.36 3.6 A LOW on this output indicates receipt of a DATA word. A HIGH indicates receipt of a COMMAND (or STATUS) word. A LOW on this input (1 sec minimum) resets the decoderto its initialized condition (same function as DEC RST), resets FAIL-SAFE, and stops and clears the transmit cycle. This function interrupts and overridesall othercontrols. -0.4 -0.4 4.0 4.0 A LOW on this output indicates receipt of a valid word. A LOW on this output, during wrap around self test only, indicates that the last word decoded was identical to the last word encoded. A HIGH on this input causes parallel tri-state I/O data on D8 through D15 to appear at the output of the first rank transmit register. A LOW locks out the register inputs. -0.4 4.0 A LOW on this output indicates the receipt of a valid command word. A LOW on this input inhibits the indication of the BROADCAST output flag. Part of 5 bit hard-wired terminal address input. Part of 5 bit herd-wired terminal address input. A 12 MHz parallel resonant crystal is connected between this input and ground. -1.0 -0.4 1.0 4.0 Output of oscillator and clock driver (see text). A LOW on this output indicates that received data is being shifted into the first rank register and is available at SERIAL DATA OUT. A LOW to HIGH transition transfers the contents of the first rank receiver register to the second rank register.
6 7
SERIAL DATA OUT ESC OUT
8 9
NC COMM / DATA SYNC
10
MRST
40
-0.8
11 12
VALID WORD BIT STATUS
13
LATCH DATA 1
20
-0.4
14 15 16 17 18 19 20
VAL CMD WD BDCST INH TMADD1* TMADD3* XTAL CLOCK OUT TAKE DATA 20 20 20 -0.4 -0.4 -0.4
SCDCT1775 Rev B
9
PIN FUNCTION AND LOADING TABLE (con't) PIN #
21
NAME
DEC RST
IIH (A)
20
IIL IOH IOL (mA) (mA) (mA)
-0.4
DESCRIPTION
A LOW on this input (1 sec minimum) resets the decoderto its initialized state, resets COMM/DATA SYNC to a LOW, and resets VALID WORD to a HIGH.
22
DSC OUT
-0.4
4.0
LOW to HIGH transitions on this output when TAKE DATA is LOW causes causes receive cycle data shifting to occur. A HIGH on this output indicates that transmit cycle data shifting is occuring. 12 MHz clock input (20pF load) (see text). A HIGH on this input enables offline wraparound selftest.The transceiver is disabled and the encoder output is connected to the decoder input (see text).
23 24 25
SEND DATA CLOCK IN S/T SELECT 1 20 .001 -0.4
-0.4
4.0
26
FAIL-SAFE
-0.4
4.0
A HIGH on this output indicates that a transmitted message has exceeded 768 sec, and that transmission has been terminated. FAIL-SAFE is reset by either FIT ENABLE or MRST. A HIGH on this output indicates receipt of a valid COMMAND word containing the correct 5 bit terminal address plus address parity. FAIL-SAFE is reset when FIT ENABLE goes HIGH. A LOW on this output indicates the reception of a valid COMMAND word whose sub-address field contains all ONES or all ZEROES. A HIGH on this input causes parallel tri-state I/O data on D0 through D7 to appear at the output of the first rank transmit register. A LOW locks out the register inputs. A LOW on this input causes the transmit cycle to start at the next HIGH to LOW transition of ESC OUT
27
RT ENABLE
-0.4
4.0
28
MODE CODE
-0.4
4.0
29
LATCH DATA 2
20
-0.4
30 31
ENCENABLE BROADCAST
20
-0.4 -0.4 4.0
A HIGH on this output indicates reception of a valid COMMAND word whose address field contains all ONES, if BDCST INH is HIGH. LSB of 5-bit hard-wired terminal address input. Part of 5-bit hard-wired terminal address input. MSB of 5-bit hard-wired terminal address input. Parity bit of hard-wired terminal address. Hard-wired for odd parity. A LOW on this input enables DATA SELECT 1, DATA SELECT 2, LATCH DATA 1, LATCH DATA 2, and ENC ENABLE inputs.
32 33 34 35 36
TMADD0* TMADD2* TMADD4* TMADDP CHAN SELECT
20 20 20 20 100
-0.4 -0.4 -0.4 -0.4 -2.0
37
ODD PARITY
-0.36
3.6
A HIGH on this output indicates a valid check for odd parity of terminal address plus parity bits, if ENA PAR CHECK is a LOW. MSB of 16 bit parallel tri-state I/O.
38
D15
20
-0.2
-12
12
SCDCT1775 Rev B
10
PIN FUNCTION AND LOADING TABLE (con't) PIN #
39 40 41 42 43 44 45 46 D13 D11 D9 D7 D5 D3 D1 LOAD DATA 2
NAME
IIH (A)
20 20 20 20 20 20 20 20
IIL IOH IOL (mA) (mA) (mA)
-0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.4 -12 -12 -12 -12 -12 -12 -12 12 12 12 12 12 12 12
DESCRIPTION
Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. LOW on this input causes the data of the D0 through D7 outputs of the first rank transmit register to be loaded into the second rank transmit register. A HIGH locks out the second rank register inputs. +5V power supply input. +12Vpower supply input. Inverted receiver input.
47 48 49 50 51 52 53
+5V +12V RX DATA IN RX STROBE TX DATA OUT CASE DATA SELECT 2 20 -0.4 40 -1.6
A LOW on this input disables the receiver output. Transmitter output. Case connection. A LOW on this input causes the output of the second rank receiver register to appear on D0 through D7 of the parallel tri-state I/O. A LOW on this input causes the output of the second rank receiver register to appear on D8 through D15 of the parallel tri-state I/O. A LOW on this input enables the function of ODD PARITY. -12 -12 -12 -12 -12 -12 -12 -12 12 12 12 12 12 12 12 12 Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. Part of 16 bit parallel tri-state I/O. LSB of 16 bit parallel tri-state I/O. A LOW on this input causes the data of the D8 through D15 outputs of the first rank transmit register to be loaded into the second rank transmit register. A HIGH locks out the second rank register inputs. Power supply and logic retum
54
DATA SELECT 1
20
-0.4
55 56 57 58 59 60 61 62 63 64
ENA PAR CHECK D14 D12 D10 D8 D6 D4 D2 D0 LOAD DATA 1
20 20 20 20 20 20 20 20 20 20
-0.4 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.4
65
GND
SCDCT1775 Rev B
11
PIN FUNCTION AND LOADING TABLE (con't) PIN #
66 67 68
NAME
-12V RX DATA IN TX DATA OUT
IIH (A)
IIL IOH IOL (mA) (mA) (mA)
DESCRIPTION
-12V power supply input. Receiver input. Inverted transmitter output.
NOTES: In the above table, the symbols are defined as follows: *Indicates use of an internal pull-up resistor. IIH = maximum input HIGH current with VIN = 2.5 volts. IIL = maximum input LOW current with VIN = 0.4 volts. IOH = maximum output HIGH current for VOUT = 2.5 volts minimum. IOL = maximum output LOW current for VOUT = 0.4 volts maximum.
SCDCT1775 Rev B
12
CT1775 PIN OUT DESCRIPTION PIN #
1 2 3 1 18 2 19 3 20 4 21 5 22 6 23 7 24 8 25 9 26 10 27 11 28 12 29 13 30 14 31 15 32 16 33 17 34 TX DATA OUT GND TX DATA OUT XTAL RXSTROBE +5V OSC/CLOCK POWER RX DATA IN CLOCK OUT RX DATA IN N/C -Vc c TAKE DATA +Vcc TX INHIBIT GND DECR ST +5V SYNC SELECT LOAD DATA 1 DSC OUT LOAD DATA 2 SERIAL DATA OUT D0 SEND DATA MIL-STD-1553B D1 ESC OUT DUMB RTU HYBRID D2 CLOCK IN D3 N/C D4 S/T SELECT D5 COMM / DATA SYNC D6 FAIL-SAFE D7 MRST D8 RT ENABLE D9 VALID WORD D10 MODE CODE D11 BIT STATUS D12 LATCH DATA 2 D13 LATCH DATA 1 D14 ENC ENABLE D15 VAL CMD WD ENA PAR CHECK BROADCAST ODD PARITY BDCST INH DATA SELECT 1 TM ADD0 CHAN SELECT TM ADD 1 DATA SELECT 2 TM ADD 2 TMADDP TM ADD 3 CASE TM ADD 4 51 68 50 67 49 66 48 65 47 64 46 63 45 62 44 61 43 60 42 59 41 58 40 57 39 56 38 55 37 54 36 53 35 52 4 5 6 7 8 9
FUNCTION
GND +5V OSC/ CLOCK PWR N/C TX INHIBIT SYNC SELECT SERIAL DATA OUT ESC OUT N/C COMM / DATA SYNC
PIN #
FUNCTION
35 TMADDP 36 CHAN SELECT 37 ODD PARITY 38 D15 39 D13 40 D11 41 D9 42 D7 43 D5 44 D3 45 D1 46 LOAD DATA 2 47 +5V 48 +Vcc 49 RX DATA IN 50 RXSTROBE 51 TX DATA OUT 52 CASE 53 DATA SELECT 2 54 DATA SELECT 1 55 ENA PAR CHECK 56 D14 57 D12 58 D10 59 D8 60 D6 61 D4 62 D2 63 D0 64 LOAD DATA 1 65 GND 66 -Vc c 67 RX DATA IN 68 TX DATAOUT
CT1775
10 MRST 11 VALIDWORD 12 BIT STATUS 13 LATCH DATA 1 14 VAL CMDWD 15 BDCST INH 16 TM ADD 1 17 TM ADD 3 18 XTAL 19 CLOCK OUT 20 TAKE DATA 21 DECR ST 22 DSC OUT 23 SEND DATA 24 CLOCK IN 25 S/T SELECT 26 FAIL-SAFE 27 RT ENABLE 28 MODE CODE 29 LATCH DATA 2 30 ENC ENABLE 31 BROADCAST 32 TM ADD 0 33 TM ADD 2 34 TM ADD 4
FIGURE 3 - PIN CONNECTION DIAGRAM, CT1775 AND PINOUT TABLE
SCDCT1775 Rev B
13
ORDERING INFORMATION MODEL NUMBER
CT1775
SCREENING
Military Temperature, -55C to +125C, Screened to the individual test methods of MIL-STD-883
POWER SUPPLY
+5V, 12V to 15V
PACKAGE
Plug in
PLUG IN PACKAGE OUTLINE
1.850
1.590 Lead 1 & ESD Designator
.100 .095
Pin 2 Pin 1
1.600
.050 Pin 16 TYP Pin 17 Pin 34 Pin 18 .018 DIA TYP
.190 MAX
1.400 1.200
Pin 68 Pin 52 Pin 51 Pin 50 .100 TYP Pin 36 Pin 35
1.600
.180 MIN
PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254
INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266
NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468
www. a e ro fl e x. com
i nfo- a ms@ a e rofl e x. com
Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied.
SCDCT1775 Rev B
Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 14

▲Up To Search▲

Price & Availability of MIL-STD-1553B

	To Download MIL-STD-1553B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .